1. Technical Field
The present invention relates to a field effect transistor and method for manufacturing thereof.
2. Related Art
For providing further sophisticated performances of field effect transistor (FET) employing gallium arsenide (GaAs), an improvement in a gate forward rising voltage (VF) is required. This is because an improvement in the VF allows providing an increased bias voltage to a gate electrode, thereby increasing a maximum drain current that can be applied to the FET. In order to enhance the VF of the FET, one of effective structures may be an adoption of a p-n junction employed right under a gate electrode exhibiting a barrier, which is higher than a Schottky barrier provided by a metal-semiconductor contact. Japanese Patent Laid-Open No. 2004-179,318 discloses a structure, which is provided with a semiconductor layer selectively doped with a high-concentration of p-type impurity in a gate opening portion at for selectively forming such p-n junction in the gate unit.
FIG. 19 is a cross-sectional view, illustrating a junction gate field effect transistor (J-FET) described in Japanese Patent Laid-Open No. 2004-179,318. An undoped aluminum gallium arsenide (AlGaAs) layer 102, a silicon (Si)-doped AlGaAs electron supply layer 103, an undoped AlGaAs spacer layer 104, an undoped indium gallium arsenide (InGaAs) channel layer 105, an undoped AlGaAs spacer layer 106, a Si-doped AlGaAs electron supply layer 107, an undoped AlGaAs layer 108 and an undoped gallium arsenide (GaAs) layer 109 are sequentially deposited on a gallium arsenide (GaAs) substrate 101. Further, an undoped AlGaAs etch stop layer 129, an undoped GaAs layer 111, a Si-doped AlGaAs wider recess stop layer 112 and a Si-doped GaAs cap layer 113 are sequentially deposited on the undoped GaAs layer 109. A source electrode 114 and a drain electrode 115 are formed on the Si dope GaAs cap layer 113.
A carbon (C)-doped p+ type GaAs layer 130 is formed in recesses formed in the undoped AlGaAs etch stop layer 129 and in the undoped GaAs layer 111. Further, a gate insulating film 116 and a gate electrode 118 are formed in recesses formed in the Si-doped AlGaAs wider recess etch stop layer 112 and in the Si-doped GaAs cap layer 113. The gate electrode 118 and the p+ type GaAs layer 130 constitutes a p-n junction.
In addition to above, prior art documents related to the present invention include: Japanese Patent Laid-Open No. 2004-282,049; Japanese Patent Laid-Open No. 2003-243,408; Japanese Patent Laid-Open No. 2002-83,816; and Japanese Patent Laid-Open No. H11-45,992 (1999).
However, a problem is arisen in the J-FET shown in FIG. 19, in which a threshold voltage (VT) is shifted before or after an energization with a gate current. FIG. 20 is a graph, showing a transmission characteristics before or after an energization with a gate current. As can be seen from the graph, it is found that the VT is shifted by 110 mV toward the positive side due to a stress caused by the energization in the J-FET of FIG. 19. The reason for causing such VT shifting is a presence of hydrogen existing in the p+ type GaAs layer 130.
A mechanism thereof is as follows. Hydrogen contained in the p+ type GaAs layer 130 is bound to carbon, which is a p-type impurity, to cause a deactivation of carbon. Thus, an effective p-type impurity concentration of the p+ type GaAs layer 130 is decreased. When an electric current is applied to the gate of the FET, electron is injected in the p+ type GaAs layer 130. Hydrogen bound to carbon is released therefrom by such injected electron to cause a reactivation of carbon, such that the effective p-type impurity concentration in the p+ type GaAs layer 130 is increased. Fermi level of the p+ type GaAs layer 130 is then moved toward the side of the valence band in response to such increase in the concentration, so that the conduction band of the channel layer is lifted, resulting in shifting the VT toward the positive side.